The present invention relates to a digital PLL (Phase Locked Loop) circuit and a signal regeneration method, and in particular, to a digital PLL circuit and a signal regeneration method which are employed in optical communication systems such as PON (Passive Optical Network) including PDS (Passive Double Star) etc.
These days, high speed and high volume data transmission is being more and more required due to development and enlargement of telecommunication techniques. In order to meet such requirements, considerable studies have been done on digital PLL circuits for quickly extracting a clock signal from burst input data signal and executing quick signal regeneration from the burst input data signal, and on signal regeneration methods utilizing such digital PLL circuits, as disclosed in Proceedings of the 1997 Electronics Society Conference of ICICE (the Institute of Electronics, Information and Communication Engineers (Japan)), C-12-25, C-12-26, Proceedings of the 1996 Electronics Society Conference of ICICE, SC-13-5, Proceedings of the 1996 Communications Society Conference of ICICE, B-844, etc.
In general, in order to realize such a high speed digital PLL circuit, digital PLL circuits are required xe2x80x9cquick extractionxe2x80x9d, that is, the capability of extracting and outputting an extracted clock signal and a regenerated data signal from burst input data signal at high speed (within a few bits).
Here, the xe2x80x9cextractionxe2x80x9d means an operation of the digital PLL circuit for extracting a regenerated data signal having no errors from the burst data signal which is inputted to the digital PLL circuit.
And a word xe2x80x9cextraction timexe2x80x9d is used in the sense that will be described below. FIGS. 1A and 1B are schematic diagrams for explaining the meaning of the word xe2x80x9cextraction timexe2x80x9d. FIG. 1A shows an input data signal which is supplied from a terminal to the digital PLL circuit, and FIG. 1B shows a regenerated data signal which has been regenerated by the digital PLL circuit from the input data signal. Referring to FIG. 1A, the input data signal includes an overhead and a data area. The overhead is provided as the preamble of the data signal and is used as training bits for the digital PLL circuit. In FIG. 1A, each bit in the data area of the input data signal is assigned a bit number, in which the assignment is started at the front end of the data area. In FIG. 1B, each bit in the data area of the regenerated data signal is also assigned a bit number in the same way. Referring to the regenerated data signal of FIG. 1B, part in the data area starting from the third bit could be regenerated by the digital PLL circuit without errors. Therefore, the xe2x80x9cextraction timexe2x80x9d in the case of FIGS. 1A and 1B is 3 bits. In the following, the important concept xe2x80x9cextraction timexe2x80x9d will be used in the sense that has been explained above.
In the following, a conventional digital PLL circuit and its signal regeneration method will be explained referring to FIG. 2. FIG. 2 is a schematic block diagram showing a conventional digital PLL circuit which has been proposed by the present inventor.
The digital PLL circuit shown in FIG. 2 comprises a data sampling section 1, a data regeneration section 3, an edge point detection operation section 4, and a clock signal extraction section 5.
The data sampling section 1 is supplied with an input data signal 10 and an N-phase clock signal 11 (N: integer larger than 1) which is composed of N clock signals whose frequencies are almost the same as the bit rate of the input data signal 10 and whose phases has been successively shifted by 1/N of the clock cycle. The data sampling section 1 digitally samples the input data signal 10 using the N-phase clock signal 11, and thereby outputs a parallel sample data signal 6 which is composed of N sample data signals.
The edge point detection operation section 4 is supplied with the parallel sample data signal 6 outputted by the data sampling section 1 and an extracted clock signal 12 which is outputted by the clock signal extraction section 5. The edge point detection operation section 4 acquires the N sample data signals of the parallel sample data signal 6 with timing in sync with the extracted clock signal 12, obtains a clock phase number which indicates the position of a rising edge in the input data signal 10 in one cycle of the extracted clock signal 12 and a clock phase number which indicates the position of a falling edge in the input data signal 10 in one cycle of the extracted clock signal 12, calculates the average of the clock phase numbers concerning the rising edges in a predetermined period till the moment and the average of the clock phase numbers concerning the falling edges in a predetermined period till the moment, obtains the number of rising edges and the number of falling edges of the input data signal 10 in one cycle of the extracted clock signal 12, and outputs an edge point operation output signal 8 which includes information on the average clock phase number concerning the rising edges, information on the average clock phase number concerning the falling edges, and information on the number of rising edges and the number of falling edges of the input data signal 10 in one cycle of the extracted clock signal 12.
The clock signal extraction section 5 is supplied with the N-phase clock signal 11 and the edge point operation output signal 8 outputted by the edge point detection operation section 4. The clock signal extraction section 5 selects a clock signal from the N clock signals composing the N-phase clock signal 11 based on the information of the edge point operation output signal 8, and outputs the selected clock signal as the extracted clock signal 12.
The data regeneration section 3 is supplied with the parallel sample data signal 6 outputted by the data sampling section 1, the edge point operation output signal 8 outputted by the edge point detection operation section 4, and the extracted clock signal 12 outputted by the clock signal extraction section 5. The data regeneration section 3 selects one sample data signal from the N sample data signals of the parallel sample data signal 6 based on the information of the edge point operation output signal 8, and outputs the selected sample data signal as a regenerated data signal 13 in sync with the extracted clock signal 12.
In the digital PLL circuit shown in FIG. 2 and its signal regeneration method, the parallel sample data signal 6 including the N sample data signals is obtained by the data sampling section 1, by digitally sampling the input data signal 10 using the N-phase clock signal 11 which is composed of N clock signals whose frequencies are almost the same as the bit rate of the input data signal 10 and whose phases has been successively shifted by 1/N of the clock cycle. Edge points of the input data signal 10 in one cycle of the extracted clock signal 12 are detected by referring to the N sample data signals of the parallel sample data signal 6 and the edge point operation output signal 8 including the information on the edge points are generated, by the edge point detection operation section 4, The extracted clock signal 12 is selected by the clock signal extraction section 5 from the N clock signals of the N-phase clock signal 11 based on the information of the edge point operation output signal 8. And one sample data signal is selected by the clock signal extraction section 5 from the N sample data signals of the parallel sample data signal 6 based on the information of the edge point operation output signal 8 and the selected sample data signal is outputted as a regenerated data signal 13 in sync with the extracted clock signal 12.
Such digital PLL circuits and signal regeneration methods are generally utilized for realizing bi-directional optical communication via optical fiber in optical communication systems such as PDS (Passive Double Star) in which terminals and base stations are connected in the shape of stars by star couplers etc.
The data signal transmitted between the base stations and the terminal by means of optical communication has the construction which has been shown in FIGS. 1A and 1B, for example. Generally, the base station transmits a data signal that includes an overhead and a data area in a burst frame, and the terminal transmits a data signal that includes an overhead that is in sync with the clock of the base station.
Such a data signal transmitted from the terminal or the base stations generally involves fluctuation such as duty distortion, jitter, frequency deviation, etc., depending on the optical path length, circuit composition, etc. Therefore, digital PLL circuits and signal regeneration methods are required resistance to such fluctuation or deterioration of the quality of the data signal.
The overhead in the data signal shown in FIGS. 1A and 1B is utilized by digital PLL circuits as training bits, as mentioned before. Therefore, signal regeneration by the digital PLL circuit can be performed more correctly if the number of bits of the overhead can be made larger. However, if long overhead is employed, the data area in one burst frame is necessitated to be small. Therefore, the digital PLL circuits and the signal regeneration methods are being required to realize the quick extraction, along with minimizing the length of the overhead and utilizing the data area efficiently.
Here, an example of the conventional digital PLL circuit which has been shown in FIG. 2 will be described more concretely. FIG.3 is a block diagram showing composition of a digital PLL circuit which has been proposed by the present inventor in Japanese Patent Application Laid-Open No. HEI8-237117. The conventional digital PLL circuit shown in FIG.3 has been designed in order to realize the quick extraction of the regenerated data signal having no errors from the burst input data which involves phase fluctuation such as duty distortion, jitter, frequency deviation, etc.
Referring to FIG. 3, the conventional digital PLL circuit comprises an input terminal 100 for receiving an input data signal 10, a data sampling circuit 123, an edge detection circuit 124, a falling edge counter 125, a clock selector 127, and a data recognition retiming circuit 128.
The data sampling circuit 123 executes digital sampling of the input data signal 10 using an N-phase clock signal 11 which is composed of N clock signals whose phases have been successively shifted by 1/N of the clock cycle and thereby obtains N sample data signals D0xcx9cDN. The edge detection circuit 124 detects varying points (referred to as xe2x80x9cedgesxe2x80x9d or xe2x80x9cedge pointsxe2x80x9d) in the input data signal 10 by referring to the sample data signals D0xcx9cDN which have been obtained by the data sampling circuit 123, and thereby outputs information 107, 109 and 110 concerning the edges. The information 107, 109 and 110 are information concerning the positions of the edge points, information concerning the number of rising edges, and information concerning the number of falling edges, which will be described below. The falling edge counter 125 calculates the average 104 of positions of falling edges which have been detected by the edge detection circuit 124 in a predetermined period. The clock selector 127 selects one clock signal from the N clock signals of the N-phase clock signal 11 and outputs the selected clock signal as an extracted clock signal 12. The data recognition retiming circuit 128 outputs a regenerated data signal 13 which is in sync with the extracted clock signal 12.
The digital PLL circuit detects edges (i.e. varying points) in the input data signal 10 in each cycle of the extracted clock signal 12 by digitally sampling the input data signal 10 using the N-phase clock signal 11 (composed of N clock signals whose phases have been successively shifted by 1/N of the clock cycle) and thereby obtaining the N sample data signals D0xcx9cDN. The extracted clock signal 12 is selected from the N clock signals of the N-phase clock signal 11 based on the result of the detection of edges in each cycle of the extracted clock signal 12. The regenerated data signal 13 is obtained by executing selection from the N sample data signals D0xcx9cDN based on the result of the detection of edges.
In the following, the operation of the digital PLL circuit of FIG. 3 will be described referring to FIG. 3 and FIG. 4.
FIG. 4 is a schematic diagram which conceptually explains the operation of the digital PLL circuit of FIG. 3. FIG. 4 shows a case where the number of phases of the N-phase clock signal 11 is 8 (i.e. N=8). Incidentally, the edge detection operation shown in FIG. 4 will also be employed in a digital PLL circuit according to the present invention.
In the case where the input data signal 10 at a moment is sampled by the data sampling circuit 123 using the 8-phase clock signal including 8 clock signals whose phases have been shifted by xe2x85x9 of the clock cycle, the sample data D0xcx9cDN which is obtained by the data sampling circuit 123 becomes a sequence of 0/1 data as shown in (A) in FIG. 4.
In the sequence of 0/1 data, a point where the sample data varies from 0 to 1 will be referred to as a rising edge point, and a point where the sample data varies from 1 to 0 will be referred to as a falling edge point.
The rising edge point and the falling edge point have to be assigned discrete numbers (integers) in order to handle the edge points digitally. Therefore, with regard to a rising edge point where the sample data varied from 0 to 1, the phase number (1, 2, 3, 4, 5, 6, 7 or 8) of a clock signal (included in the 8-phase clock signal) with which the sample data varied to 1 (xe2x80x9c2xe2x80x9d in (A) of FIG. 4) is assigned to the rising edge point. On the other hand, with regard to a falling edge point where the sample data varied from 1 to 0, the phase number of a clock signal (included in the 8-phase clock signal) with which the sample data varied to 0 (xe2x80x9c7xe2x80x9d in (A) of FIG. 4) is assigned to the falling edge point.
The edge detection circuit 124 executes detection of edge points according to the method described above. The edge detection circuit 124 also obtains the number of rising edge points in one cycle of the extracted clock signal 12 and the number of falling edge points in one cycle of the extracted clock signal 12. The edge detection circuit 124 outputs the clock phase number information 107 concerning the edge points to the falling edge counter 125, and outputs the information 109 on the number of rising edge points in a cycle of the extracted clock signal 12 and the information 110 on the number of falling edge points in a cycle of the extracted clock signal 12 to the data recognition retiming circuit 128.
The falling edge counter 125, which received the clock phase number information 107, obtains the average of the clock phase numbers of falling edge points in a predetermined period till the moment.
Here, if the input data signal 10 has no phase fluctuation such as duty distortion, jitter, etc., there is no need to take the average by the falling edge counter 125. However, as a matter of fact, the input data signal 10 generally involves phase fluctuation due to jitter, duty distortion, etc., and thus the clock phase number of the rising edge point and the clock phase number of the falling edge point vary with time. Therefore, the falling edge counter 125 takes the average of the clock phase numbers of falling edge points in a predetermined period till the moment. As shown in FIG. 4, such an average is not an integer, and thus the average is rounded off to the nearest integer. Incidentally, the average of phase numbers is taken by the falling edge counter 125 between falling edges, and thus the average phase number is updated when a new falling edge is detected in the sample data signals D0xcx9cDN.
The averaging by the falling edge counter 125 is executed in order to obtain the phase of the center point of jitter (fluctuation with time) of the falling edges in the input data signal 10. Therefore, when the phase of the center point of the jitter varied at a low speed, the average taken by the falling edge counter 125 varies following the variation.
The averaging by the falling edge counter 125 has a meaning of suppressing the jitter of the edge points in the input data signal 10. In the operation of the digital PLL circuit, by the averaging, high frequency components of the jitter is suppressed (ignored) and low frequency components of the jitter is not ignored, and thus the digital PLL circuit follows the low speed variation of the edge points.
The falling edge counter 125 outputs the average 104, that is, information on the average phase number (average position) of the falling edges to the clock selector 127.
The clock selector 127 selects a clock signal that corresponds to the average 104 from the N clock signals in the N-phase clock signal 11, and outputs the selected clock signal to the data sampling circuit 123, the data recognition retiming circuit 128 and outside, as the extracted clock signal 12.
The extracted clock signal 12 selected by the clock selector 127 is used by the data recognition retiming circuit 128 for the selection of the regenerated data signal 13 from the N sample data signals D0xcx9cDN.
The data recognition retiming circuit 128 is supplied with the information 109 on the number of rising edge points and the information 110 on the number of falling edge points which are outputted by the edge detection circuit 124, the N sample data signals D0xcx9cDN which are outputted by the data sampling circuit 123, and the extracted clock signal 12 which is outputted by the clock selector 127.
In the following, the data regeneration operation of the data recognition retiming circuit 128 will be described referring to FIG. 5. FIG. 5 is a schematic diagram which conceptually explains the data regeneration operation of the data recognition retiming circuit 128. Incidentally, the concept of the data regeneration operation shown in FIG. 5 will also be employed in the digital PLL circuit according to the present invention.
As shown in FIG.5, the data regeneration operation of the data recognition retiming circuit 128 is controlled depending on the number of edge points in one cycle T of the extracted clock signal 12. The data recognition retiming circuit 128 is supplied with the information 109 on the number of rising edge points in a cycle T of the extracted clock signal 12 and the information 110 on the number of falling edge points in a cycle T of the extracted clock signal 12 from the edge detection circuit 124 as shown in FIG. 3, and the data recognition retiming circuit 128 determines the value of the regenerated data signal 13 utilizing the information 109 and 110.
For example, in the case where the number of edge points in a cycle T of the extracted clock signal 12 is 0, the input data signal 10 should have had a constant value 0 or 1 during the cycle T (pattern (A) in FIG. 5). Therefore, any one of the N sample data signals D0xcx9cDN during the cycle T of the extracted clock signal 12 can be selected as the regenerated data signal 13.
In the case where the number of edge points in a cycle T of the extracted clock signal 12 is 2, the input data signal 10 should have had one convex pulse (rising edge+falling edge) or one concave pulse (falling edge+rising edge) during the cycle T (pattern (B) in FIG. 5). Therefore, one of the N sample data signals D0xcx9cDN just after the first edge point in the cycle T is selected as the regenerated data signal 13. Concretely, in the case where the first edge point in the cycle T is a rising edge point as shown in xe2x80x9cb1xe2x80x9d of FIG. 5, data during the cycle T is judged to be 1. On the other hand, in the case where the first edge point in the cycle T is a falling edge point as shown in xe2x80x9cb2xe2x80x9d of FIG. 5, data during the cycle T is judged to be 1.
In the case where the number of edge points in a cycle T of the extracted clock signal 12 is 1, the input data signal 10 should have had changed its value from 1 to 0 or from 0 to 1 during the cycle T (pattern (C) in FIG. 5). In the case where the edge point in the cycle T is a falling edge point, the data recognition retiming circuit 128 judges that data during the cycle T is 0 if the position of the falling edge point is on the left side of the center of the cycle T, and judges that data during the cycle T is 1 if the position of the falling edge point is on the right side of the center of the cycle T. On the other hand, in the case where the edge point in the cycle T is a rising edge point, the data recognition retiming circuit 128 judges that data during the cycle T is 1 if the position of the rising edge point is on the left side of the center of the cycle T, and judges that data during the cycle T is 0 if the position of the rising edge point is on the right side of the center of the cycle T.
The data recognition retiming circuit 128 outputs the regenerated data signal 13 which is in sync with the extracted clock signal 12, according to the data regeneration operation described above.
As described above, in the digital PLL circuit and the signal regeneration method which have been proposed by the present inventor in Japanese Patent Application Laid-Open No. HEI8-237117, even if the phase of the input data signal 10 fluctuated due to jitter etc., the input data signal 10 is digitally sampled using the N-phase clock signal 11 and the average phase number of edge points of the input data signal 10 is obtained by referring to the N sample data signals D0xcx9cDN. The extracted clock signal 12 is selected from the N clock signals of the N-phase clock signal 11 based on the average phase number of edge points. The data recognition is executed by selecting one sample data signal from the N sample data signals D0xcx9cDN as the regenerated data signal 13 based on the information 109 and 110 concerning the number of edge points in one cycle of the extracted clock signal 12. The regenerated data signal 13 as the result of the data recognition is outputted with timing in sync with the extracted clock signal 12.
Therefore, according to the digital PLL circuit and the signal regeneration method, for the input of the burst input data signal 10 which involves phase fluctuation due to frequency deviation, duty distortion, jitter, etc, a clock signal in the N-phase clock signal 11 that is in sync with the input data signal 10 can be extracted as the extracted clock signal 12, and data to which data recognition and re-timing has been executed with no errors can be obtained as the regenerated data signal 13, with quick extraction, that is, in a short time within a few bits.
However, the speed of the extraction by the digital PLL circuit and the signal regeneration method which have been described above is not enough, and a digital PLL circuit and a signal regeneration method, which can realize quicker extraction along with maximum usage efficiency of the data area of the data signal and enough resistance to jitter and duty distortion of the input data signal at a low cost, are now being required.
However, in the conventional digital PLL circuit and the signal regeneration method described above, the xe2x80x9cquick extractionxe2x80x9d is incompatible with the xe2x80x9cefficient use of the data areaxe2x80x9d, and the xe2x80x9cquick extractionxe2x80x9d is incompatible with the xe2x80x9cresistance to jitter and duty distortion of the input data signalxe2x80x9d, and thus it has been impossible to provide such a digital PLL circuit and a signal regeneration method which can realize quicker extraction, maximum usage efficiency of the data area, and enough resistance to jitter and duty distortion of the input data signal.
In the following, the relationship between the xe2x80x9cquick extractionxe2x80x9d and the xe2x80x9cefficient use of the data areaxe2x80x9d, and the relationship between the xe2x80x9cquick extractionxe2x80x9d and the xe2x80x9cresistance to jitter and duty distortionxe2x80x9d in the conventional digital PLL circuit and signal regeneration method will be explained.
First, the relationship between the xe2x80x9cquick extractionxe2x80x9d and the xe2x80x9cefficient use of the data areaxe2x80x9d will be described. In the conventional digital PLL circuit and signal regeneration method described above, in order to shorten the extraction time (decrease the number of error bits in the data area of the regenerated data signal), one solution is to increase the number of bits of the overhead (shown in FIGS. 1A and 1B) which is utilized for clock recovery etc. By increasing the number of bits of the overhead, the number of bits (in the data area of the regenerated data signal) which can include errors becomes small, and thus the xe2x80x9cquick extractionxe2x80x9d can be realized. However, part of the data signal that can be utilized as the data area is necessitated to be small due to the increasing of the number of bits of the overhead. Therefore, the xe2x80x9cquick extractionxe2x80x9d and the xe2x80x9cefficient use of the data areaxe2x80x9d are antinomy and incompatible with each other.
Next, the relationship between the xe2x80x9cquick extractionxe2x80x9d and the xe2x80x9cresistance to jitter and duty distortionxe2x80x9d will be described. In the conventional digital PLL circuit and signal regeneration method described above, in order to improve resistance to jitter or resistance to duty distortion, the amount of phase correction with respect to phase fluctuation in the input data signal should be made small, and feedback control should be executed with small feedback gain. However, in such a feedback circuit having relatively small feedback gain in comparison with the phase fluctuation in the input data signal, phase correction per one phase comparison becomes small, and thus the extraction time is necessitated to be long.
On the other hand, in order to shorten the extraction time, feedback control against the phase fluctuation in the input data signal should be executed with large feedback gain. However, in such a feedback circuit having relatively large feedback gain in comparison with the phase fluctuation in the input data signal, the extracted phase information follows wildly to the jitter and the duty distortion, or might start oscillating, and thereby data recognition errors are caused. Therefore, the resistance to jitter and the resistance to duty distortion are necessitated to be decreased.
Therefore, the xe2x80x9cquick extractionxe2x80x9d and the xe2x80x9cresistance to jitter and duty distortionxe2x80x9d are antinomy and incompatible with each other in the conventional digital PLL circuit and signal regeneration method, and thus an attempt to shorten the extraction time lowers the resistance to jitter and duty distortion, and errors occur in the regenerated data signal.
It is therefore the primary object of the present invention to provide a digital PLL circuit and a signal regeneration method which can realize the quicker extraction along with the efficient use of the data area and the resistance to jitter and duty distortion of the input data signal.
In accordance with a first aspect of the present invention, there is provided a digital PLL circuit comprising a data sampling means, an edge point detection operation means, a clock signal extraction means, a delay means, and a data regeneration means. The data sampling means is supplied with an input data signal and an N-phase clock signal (N: integer larger than 1) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle. The data sampling means digitally samples the input data signal using the N clock signals and thereby outputs a parallel sample data signal including N sample data signals. The edge point detection operation means acquires the N sample data signals of the parallel sample data signal, detects edge points in the acquired N sample data signals in one cycle of an extracted clock signal, and outputs an edge point operation output signal which includes information on the edge points in one cycle of the extracted clock signal. The clock signal extraction means is supplied with the N-phase clock signal and the edge point operation output signal outputted by the edge point detection operation means. The clock signal extraction means selects a clock signal from the N clock signals of the N-phase clock signal based on the information of the edge point operation output signal and outputs the selected clock signal as the extracted clock signal. The delay means delays the N sample data signals of the parallel sample data signal supplied from the data sampling means and thereby outputs a parallel delayed sample data signal including N delayed sample data signals. The data regeneration means is supplied with the parallel delayed sample data signal outputted by the delay means and the edge point operation output signal outputted by the edge point detection operation means. The data regeneration means selects a delayed sample data signal from the N delayed sample data signals of the parallel delayed sample data signal based on the information of the edge point operation output signal and outputs the selected delayed sample data signal as a regenerated data signal.
In accordance with a second aspect of the present invention, in the first aspect, the extracted clock signal extracted by the clock signal extraction means is outputted to the outside of the digital PLL circuit.
In accordance with a third aspect of the present invention, in the first aspect, the delay time of the delay means is set so that time necessary for obtaining the extracted clock signal based on a parallel sample data signal will not become longer than time necessary for obtaining the regenerated data signal from the parallel sample data signal.
In accordance with a fourth aspect of the present invention, in the first aspect, the delay means delays the N sample data signals of the parallel sample data signal keeping phase differences between the N sample data signals.
In accordance with a fifth aspect of the present invention, in the first aspect, the delay means includes N flip-flop lines each of which including M stages of flip-flops (M: natural number). Each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by M bits.
In accordance with a sixth aspect of the present invention, in the first aspect, the delay means includes a 1/L frequency demultiplier for demultiplying the frequencies of the N clock signals of the N-phase clock signal by L (L: integer larger than 1) and N flip-flop lines each of which including M stages of flip-flops (M: natural number). Each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal whose frequency has been demultiplied by the 1/L frequency demultiplier to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by Mxc3x97L bits.
In accordance with a seventh aspect of the present invention, in the first aspect, the edge point operation output signal outputted by the edge point detection operation means includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a rising edge of the input data signal.
In accordance with an eighth aspect of the present invention, in the first aspect, the edge point operation output signal outputted by the edge point detection operation means includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a falling edge of the input data signal.
In accordance with a ninth aspect of the present invention, in the seventh aspect, the edge point operation output signal outputted by the edge point detection operation means includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.
In accordance with a tenth aspect of the present invention, in the eighth aspect, the edge point operation output signal outputted by the edge point detection operation means includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.
In accordance with an eleventh aspect of the present invention, in the seventh aspect, the edge point operation output signal outputted by the edge point detection operation means includes information on the average of the phase numbers that indicate the rising edges of the input data signal in a predetermined period.
In accordance with a twelfth aspect of the present invention, in the eighth aspect, the edge point operation output signal outputted by the edge point detection operation means includes information on the average of the phase numbers that indicate the falling edges of the input data signal in a predetermined period.
In accordance with a thirteenth aspect of the present invention, in the first aspect, the edge point detection operation means acquires the N sample data signals of the parallel sample data signal with timing in sync with the extracted clock signal.
In accordance with a fourteenth aspect of the present invention, in the eleventh aspect, the clock signal extraction means utilizes the information on the average of the phase numbers that indicate the rising edges of the input data signal for the selection of the extracted clock signal.
In accordance with a fifteenth aspect of the present invention, in the twelfth aspect, the clock signal extraction means utilizes the information on the average of the phase numbers that indicate the falling edges of the input data signal for the selection of the extracted clock signal.
In accordance with a sixteenth aspect of the present invention, in the first aspect, the data regeneration means is supplied with the extracted clock signal outputted by the clock signal extraction means, and outputs the regenerated data signal with timing in sync with the extracted clock signal.
In accordance with a seventeenth aspect of the present invention, there is provided a digital PLL circuit which digitally samples an input data signal using an N-phase clock signal (N: integer larger than 1) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle and thereby obtains a parallel sample data signal including N sample data signals, detects edge points of the input data signal in one cycle of an extracted clock signal by referring to the N sample data signals of the parallel sample data signal, obtains the extracted clock signal by selecting one clock signal from the N clock signals of the N-phase clock signal based on the result of the detection of the edge points, obtains a regenerated data signal by executing selection from signals corresponding to the N sample data signals of the parallel sample data signal based on the result of the detection of the edge points, and outputs the regenerated data signal. In the digital PLL circuit, the N sample data signals of the parallel sample data signal are delayed by a delay means and thereby a parallel delayed sample data signal including N delayed sample data signals is obtained, and the selection for obtaining the regenerated data signal is executed from the N delayed sample data signals of the parallel delayed sample data signal.
In accordance with an eighteenth aspect of the present invention, in the seventeenth aspect, the extracted clock signal is outputted to the outside of the digital PLL circuit.
In accordance with a nineteenth aspect of the present invention, in the seventeenth aspect, the delay time of the delay means is set so that time necessary for obtaining the extracted clock signal based on a parallel sample data signal will not become longer than time necessary for obtaining the regenerated data signal from the parallel sample data signal.
In accordance with a twentieth aspect of the present invention, in the seventeenth aspect, the delay means delays the N sample data signals of the parallel sample data signal keeping phase differences between the N sample data signals.
In accordance with a twenty-first aspect of the present invention, in the seventeenth aspect, the delay means includes N flip-flop lines each of which including M stages of flip-flops (M: natural number). Each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by M bits.
In accordance with a twenty-second aspect of the present invention, in the seventeenth aspect, the delay means includes a 1/L frequency demultiplier for demultiplying the frequencies of the N clock signals of the N-phase clock signal by L (L: integer larger than 1) and N flip-flop lines each of which including M stages of flip-flops (M: natural number). Each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal whose frequency has been demultiplied by the 1/L frequency demultiplier to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by Mxc3x97L bits.
In accordance with a twenty-third aspect of the present invention, in the seventeenth aspect, the result of the detection of the edge points includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a rising edge of the input data signal.
In accordance with a twenty-fourth aspect of the present invention, in the seventeenth aspect, the result of the detection of the edge points includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a falling edge of the input data signal.
In accordance with a twenty-fifth aspect of the present invention, in the twenty-third aspect, the result of the detection of the edge points includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.
In accordance with a twenty-sixth aspect of the present invention, in the twenty-fourth aspect, the result of the detection of the edge points includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.
In accordance with a twenty-seventh aspect of the present invention, in the twenty-third aspect, the result of the detection of the edge points includes information on the average of the phase numbers that indicate the rising edges of the input data signal in a predetermined period.
In accordance with a twenty-eighth aspect of the present invention, in the twenty-fourth aspect, the result of the detection of the edge points includes information on the average of the phase numbers that indicate the falling edges of the input data signal in a predetermined period.
In accordance with a twenty-ninth aspect of the present invention, in the seventeenth aspect, the regenerated data signal is outputted with timing in sync with the extracted clock signal.
In accordance with a thirtieth aspect of the present invention, there is provided a signal regeneration method comprising the steps of: a data sampling step, an edge point detection operation step, a clock signal extraction step, a delay step, and a data regeneration step. In the data sampling step, an input data signal is digitally sampled using an N-phase clock signal (N: integer larger than 1) including N clock signals whose frequencies are almost the same as the bit rate of the input data signal and whose phases has been successively shifted by 1/N of the clock cycle, and thereby a parallel sample data signal including N sample data signals is obtained. In the edge point detection operation step, the N sample data signals of the parallel sample data signal are acquired, edge points in the acquired N sample data signals in one cycle of an extracted clock signal are detected, and an edge point operation output signal which includes information on the edge points in one cycle of the extracted clock signal is generated. In the clock signal extraction step, the extracted clock signal is selected from the N clock signals of the N-phase clock signal based on the information of the edge point operation output signal. In the delay step, the N sample data signals of the parallel sample data signal are delayed and thereby a parallel delayed sample data signal including N delayed sample data signals are obtained. And in the data regeneration step, a delayed sample data signal is selected from the N delayed sample data signals of the parallel delayed sample data signal based on the information of the edge point operation output signal and the selected delayed sample data signal is outputted as a regenerated data signal.
In accordance with a thirty-first aspect of the present invention, in the thirtieth aspect, the extracted clock signal is outputted to the outside of the device that employs the signal regeneration method.
In accordance with a thirty-second aspect of the present invention, in the thirtieth aspect, the delay time of the delay step is set so that time necessary for obtaining the extracted clock signal based on a parallel sample data signal will not become longer than time necessary for obtaining the regenerated data signal from the parallel sample data signal.
In accordance with a thirty-third aspect of the present invention, in the delay step of the thirtieth aspect, the N sample data signals of the parallel sample data signal are delayed keeping phase differences between the N sample data signals.
In accordance with a thirty-fourth aspect of the present invention, in the thirtieth aspect, the delay step is executed by a delay means which includes N flip-flop lines each of which including M stages of flip-flops (M: natural number), in which each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by M bits.
In accordance with a thirty-fifth aspect of the present invention, in the thirtieth aspect, the delay step is executed by a delay means which includes a 1/L frequency demultiplier for demultiplying the frequencies of the N clock signals of the N-phase clock signal by L (L: integer larger than 1) and N flip-flop lines each of which including M stages of flip-flops (M: natural number), in which each flip-flop line is supplied with corresponding one of the N clock signals of the N-phase clock signal whose frequency has been demultiplied by the 1/L frequency demultiplier to clock terminals of its M flip-flops and delays corresponding one of the N sample data signals of the parallel sample data signal by Mxc3x97L bits.
In accordance with a thirty-sixth aspect of the present invention, in the thirtieth aspect, the edge point operation output signal generated in the edge point detection operation step includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a rising edge of the input data signal.
In accordance with a thirty-seventh aspect of the present invention, in the thirtieth aspect, the edge point operation output signal generated in the edge point detection operation step includes information on the phase number of a clock signal in the N clock signals of the N-phase clock signal that indicates a falling edge of the input data signal.
In accordance with a thirty-eighth aspect of the present invention, in the thirty-sixth aspect, the edge point operation output signal generated in the edge point detection operation step includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.
In accordance with a thirty-ninth aspect of the present invention, in the thirty-seventh aspect, the edge point operation output signal generated in the edge point detection operation step includes information on the number of edge points of the input data signal in one cycle of the extracted clock signal.
In accordance with a fortieth aspect of the present invention, in the thirty-sixth aspect, the edge point operation output signal generated in the edge point detection operation step includes information on the average of the phase numbers that indicate the rising edges of the input data signal in a predetermined period.
In accordance with a forty-first aspect of the present invention, in the thirty-seventh aspect, the edge point operation output signal generated in the edge point detection operation step includes information on the average of the phase numbers that indicate the falling edges of the input data signal in a predetermined period.
In accordance with a forty-second aspect of the present invention, in the edge point detection operation step of the thirtieth aspect, the N sample data signals of the parallel sample data signal are acquired with timing in sync with the extracted clock signal.
In accordance with a forty-third aspect of the present invention, in the fortieth aspect, the information on the average of the phase numbers that indicate the rising edges of the input data signal is utilized for the selection of the extracted clock signal in the clock signal extraction step.
In accordance with a forty-fourth aspect of the present invention, in the forty-first aspect, the information on the average of the phase numbers that indicate the falling edges of the input data signal is utilized for the selection of the extracted clock signal in the clock signal extraction step.
In accordance with a forty-fifth aspect of the present invention, in the data regeneration step of the thirtieth aspect, the regenerated data signal is outputted with timing in sync with the extracted clock signal.